1. Field of the Invention
The present invention relates to integrated network devices having Peripheral Component Interconnect (PCI) bridges.
2. Background Art
Peripheral Component Interconnect (PCI) interfaces have been used to provide high-speed connectivity between devices in a multi-device system, such as a processor based system such as a personal computer.
FIG. 1 is a diagram illustrating a conventional implementation of a PCI bus system architecture 100. The system 100 includes a processor 102 coupled to a memory controller 104 via a local bus 106. The processor 102 and the memory controller 104 are coupled to a PCI local bus 106 (labeled PCI Local Bus #0) via a host bridge 108.
The host bridge 108 provides a low latency path through which the processor 102 may directly access PCI devices 110, for example a network interface card 110a providing access to a local area network, a disc drive (SCSI) controller 110b providing access to disk drives 114, an audio card 110c, a motion picture card 110d, or a graphics card 110e configured for driving a monitor 116. The host bridge 108 also provides a high bandwidth path allowing PCI masters on the PCI bus 106 direct access to the system memory 118 via the memory controller 104. A cache memory 120 is independent of the system memory 118 for use by the processor 102.
The term “host bridge” refers to the bridge device 108 that provides access to the system memory 118 for the devices 110 connected to the PCI bus 106. A PCI-to-PCI bridge 122 also may be used to connect a second PCI bus 124 to the PCI bus 106, the second PCI bus 124 configured for connecting other I/O devices 126.
Newer PCI bus protocols are being published, including PCI-X Mode 2, that provide enhanced PCI functionality. These newer PCI bus protocols include the PCI Local Bus Specification, Rev 2.3, the PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev. 2.0a, and the PCI-to-PCI Bridge Architecture Specification, Rev 1.2.
The PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification Revision 2.0a, Aug. 22, 2003 (hereinafter “PCI-X E/M Addendum”), specifically “Appendix C—PCI-X Mode 2 Device Design Guidelines and Examples” describes on pages 123-132 a proposal for implementing Double Data Rate (DDR) and Quad Data Rate (QDR) transmissions. In particular, the PCI data on the PCI-X bus is edge triggered (i.e., data is valid on the PCI-X bus when the PCI clock transitions from one state to another), such that the PCI data is latched on each rising and falling clock edge.
The implementation as suggested in the Appendix C suffers from the disadvantage that the disclosed technique for latching incoming data from the PCI-X bus creates numerous timing synchronization problems. According to the proposed implementation, multiple flip-flops inside the PCI device are arranged into an array for storing the incoming PCI data, where a selected flip-flop is used for latching a corresponding PCI data bit: decision logic outputs a signal used as the clock for latching the data into the selected flip-flop.
However, the proposed implementation as suggested in the Appendix C suffers from the disadvantage that the timing within the device is harder to predict, resulting in timing synchronization problems during implementation, for example due to implementation variations such as aligning strobe signals with the data, differences in board wire lengths, duty cycle variations, variations between drivers, and data pattern intersymbol interference.